In September, we introduced the cascade solution for embedding iris recognition into edge devices: deep network inference on FPGA boards relied on the Vitis AI toolchain and DPU acceleration core provided by FPGA manufacturers. Two months later, there is a new answer to this link — RDPU, the self-developed deep learning inference acceleration core by Homsh R&D Center, has successfully run the full iris recognition model on FPGA boards.
On October 26, the 512-byte full-network features generated by the RegNetX iris recognition model on RDPU were compared byte by byte with the simulator baseline, showing zero difference. On October 30, the 100 MHz version passed on-board verification: 30 consecutive inference runs produced completely consistent results, and feature extraction and matching were completed for all 200 iris images. From the instruction set to hardware circuits, and then to the compilation toolchain, this "AI heart" is entirely built by us.
For deep learning inference on Xilinx FPGAs, the standard industry practice is to use AMD’s (formerly Xilinx’s) Vitis AI to quantize and compile models, which are then executed by the official DPU acceleration core. This approach is mature and practical, and it was the path Homsh took for previous edge solutions.
However, general-purpose acceleration cores are designed to support all kinds of networks, while iris recognition has its own specific requirements: unique network structures, strict constraints on resources and power consumption for end-side devices, and our long-term plan to port this capability to more hardware platforms and even self-developed chips. All of these call for an inference hardware layer fully under our own control. RDPU is exactly that layer.
Two on-board paths for the same iris model. RDPU replaces the middle two layers: the compilation toolchain and the inference core.
RDPU is a deep learning acceleration core designed for INT8 inference, running on the AXU9EB FPGA board based on Zynq UltraScale+ MPSoC. It features a custom instruction set supporting operators including convolution, element-wise addition, max pooling, global average pooling, fully connected layers and channel-wise operations, covering all requirements of mainstream iris recognition networks. Its hardware circuits are independently designed and implemented by the team in RTL.
Supporting the core is a complete self-developed software chain: the compilation toolchain quantizes trained models into INT8 format, maps them into RDPU instruction sequences and packages them into model images; the on-board system loads the hardware and model under embedded Linux, and directly outputs 512-dimensional iris features. Every layer from model to features is fully controlled by us, and related core technologies have been filed for intellectual property protection simultaneously.
● Networks running on-board: 4 types
● Iris feature vector: 512 dimensions
● Byte-by-byte comparison with baseline: 0 difference
RDPU’s on-board implementation has been advanced model by model. First, the full ResNet-18 INT8 pipeline was completed, marking the first time the self-developed core output correct results on board. Then, the lightweight feature network achieved 66.13 FPS in 200 consecutive on-board tests on RDPU — the feature inference performance alone is more than double the 30 FPS design target.
On October 10, the hundred-layer IResNet100 generated 512-dimensional iris features on RDPU, reaching a cosine similarity of 0.9977 with the software reference; in a small-scale test gallery, the similarity scores for genuine pairs and impostor pairs were clearly separated. For the RegNetX iris recognition model, the team identified and resolved every deviation through layer-by-layer verification, finally achieving byte-level consistency between the full-network output and the simulator baseline.
For the grouped convolutions widely used in iris models, RDPU adopts dedicated structural optimization: static weight read volume drops from approximately 125 million bytes to around 5.67 million bytes, a reduction of about 95.5%, and multiply-add instruction issuance decreases by approximately 76.9%. This is exactly the value of a self-developed core — hardware can be tailored to our specific models.
RDPU on-board milestones. FPS refers only to the feature inference stage, excluding iris localization, polar coordinate normalization and identity matching.
As always, we state uncertainties openly. The 66.13 FPS result is for the lightweight feature network; for larger models like IResNet100 and RegNetX, RDPU has achieved full functionality and aligned results, but at the current 100 MHz clock frequency, there is still a noticeable gap to real-time recognition. This is the key challenge to tackle in the next phase.
The direction is clear: first, optimize convolution data fetching and memory access scheduling based on per-instruction performance counters to reduce data waiting time for computing units; second, advance the 325 / 650 MHz multi-clock multiply-add array — the 32×32 array prototype has completed 1,000 transaction comparisons in simulation, and timing closure and on-board verification are in progress; third, extend the real-time target from feature inference to the full pipeline of localization, normalization and matching.
Three main priorities for the next phase: data supply, multi-clock array, and full-pipeline real-time performance.
From self-developed iris recognition algorithms, to software-hardware co-optimized FPGA solutions, and now to our own AI inference core design, Homsh has been delving deeper into the technology stack. The successful running of the full iris recognition model on RDPU marks the most difficult first step we have taken — from "using others’ acceleration cores" to "having our own".
Functional alignment is only the starting point; meeting performance targets is the final goal. We will continue to share every progress honestly, along with its current limitations.
Three key figures: zero difference between RegNetX full-network output and baseline; 66.13 FPS for lightweight feature network; 95.5% reduction in grouped convolution weight reads.
